1. Field of the Invention
The present invention relates to a semiconductor package where a functional element formed on a first surface of an element substrate is sealed in a closed space. The present invention also relates to a method of producing the semiconductor package and a semiconductor package assembly.
2. Description of the Related Art
A wafer level package is known as a semiconductor package where a semiconductor element formed on a surface of a semiconductor element substrate is sealed in a closed space. In the above wafer level package, a substrate has a junction with a wafer formed with the semiconductor element, to thereby seal the semiconductor element in the closed space. Japanese Patent Application Laid-Open No 2005-251898 (=JP2005251898) discloses a conventional technology of a method of using solder for causing the substrate to have the junction with the wafer.
In the conventional wafer level package according to the JP2005251898, however, the solder is applied in such a manner as to surround the semiconductor element for the junction between the substrate and the wafer. By the way, the solder for the junction between the substrate and the wafer is made of metal. Therefore, for preventing the solder (for the above junction) from contacting an electrode pad of the semiconductor element, the solder and the electrode pad should be spaced apart. Therefore, the wafer level package according to the JP2005251898 is large, which is inconvenient.